Chapter 5: CCP Modules
The abbreviation CCP stands for Capture/Compare/PWM.The CCP module is a peripheral which allows the user to time and control different events.
Capture Mode, allows timing for the duration of an event. This circuit gives insight into the current state of a register which constantly changes its value. In this case, it is the timer TMR1 register.
Compare Mode compares values contained in two registers at some point. One of them is the timer TMR1 register. This circuit also allows the user to trigger an external event when a predetermined amount of time has expired.
PWM - Pulse Width Modulation can generate signals of varying frequency and duty cycle.
The PIC16F887 microcontroller has two such modules - CCP1 and CCP2.
Both of them are identical in normal mode, with the exception of the Enhanced PWM features available on CCP1 only. This is why this chapter describes the CCP1 module in detail. Concerning CCP2, only the features distinguishing it from CCP1 will be covered.
Complicated? All this is only a simplified explanation on their operation. Everything is much more complicated in practice because these modules can operate in many different modes. Try to analyze their operation on the basis of the tables describing bit functions. If you use any CCP module, first select the mode you need, analyze the appropriate figure and then start changing bits of the registers or else...
CCP1 Module
A central part of this circuit is a 16-bit register CCPR1, which consists of the CCPR1L and CCPR1H registers. It is used for capturing or comparing with binary number stored in the timer register TMR1 (TMR1H and TMR1L).
Fig. 5-1 CCP1 Module
Bits of the CCP1CON register controls the CCP1 module.
CCP1 in Capture mode
In this mode, the timer register TMR1 (consisting of TMR1H and TMR1L) is copied to the CCP1 register (consisting of CCPR1H and CCPR1L) in the following situations:- Every falling edge (1 » 0) on the RC2/CCP1 pin;
- Every rising edge (0 » 1) on the RC2/CCP1 pin;
- Every 4th rising edge (0 » 1) on the RC2/CCP1 pin; and
- Every 16th rising edge (0 » 1) on the RC2/CCP1 pin.
- RC2/CCP1 pin must be configured as input; and
- TMR1 module must operate as timer or synchronous counter.
Fig. 5-2 CCP1 in Capture mode
When the Capture mode is changed, an undesirable capture interrupts may be generated. In order to avoid that, both a bit enabling CCP1IE interrupt and flag bit CCP1IF should be cleared prior to any change occuring in the control register.
Undesirable interrupt may be also generated by switching from one capture prescaler to another. To avoid this, the CCP1 module should be temporarily switched off before changing the prescaler.
The following program sequence is recommended:
BANKESEL CCP1CON CLRF CCP1CON ;CONTROL REGISTER IS CLEARED ;CCP1 MODULE IS OFF MOVLW XX ;NEW PRESCALER MODE IS SELECTED MOVWF CCP1CON ;NEW VALUE IS LOADED TO THE CONTROL REGISTER ;CCP1 MODULE IS SIMULTANEOUSLY SWITCHED ON
CCP1 in Compare mode
In this mode, the value in the CCP1 register is constantly compared to the value in the timer register TMR1. When a match occurs, the output pin RC2/CCP1 logic state may be changed, which depends on the state of bits in the control register (CCP1M3 - CCP1M0). The flag-bit CCP1IF will be simultaneously set.
Fig. 5-3 CCP1 in Compare mode
- Pin RC2/CCP1 must be configured as output; and
- Timer TMR1 must be synchronized with internal clock.
CCP1 in PWM mode
Signals of varying frequency and duty cycle have a wide application in automation. A typical example is a power control circuit whose simple operation is shown in figure 5-4 below. If a logic zero (0) represents switch-off and logic one (1) represents switchon, the power that the load consumes will be directly proportional to the pulse duration. This ratio is often called Duty Cycle.
Fig. 5-4 CCP1 in PWM mode
Fig. 5-5 CCP1 in PWM mode with filtration
Fig. 5-6 PWM module
Fig.5-7 PWM Mode
PWM Period
The output pulse period (T) is specified by the PR2 register of the timer TMR2. The PWM period can be calculated using the following equation:PWM Period(T) = (PR2 +1) * 4Tosc * TMR2 Prescale Value
If the PWM Period (T) is known then, it is easy to determine the signal frequency F because these two values are related by equation F=1/T.
PWM Duty Cycle
The PWM duty cycle is specified by using in total of 10 bits: eight MSbs found in the CCPR1L register and two additional LSbs found in the CCP1CON register (DC1B1 and DC1B0). The result is 10-bit number contained in the formula:Pulse Width = (CCPR1L,DC1B1,DC1B0) * Tosc * TMR2 Prescale Value
The following table shows how to generate PWM signals of varying frequency if the microcontroller uses 20 MHz quartz-crystal (Tosc=50nS).
| Frequency [KHz] | 1.22 | 4.88 | 19.53 | 78.12 | 156.3 | 208.3 |
|---|---|---|---|---|---|---|
| TMR2 Prescaler | 16 | 4 | 1 | 1 | 1 | 1 |
| PR2 Register | FFh | FFh | FFh | 3Fh | 1Fh | 17h |
Table 5-1 PWM Duty Cycle
At last, two notes:- Output pin will be constantly set in case the pulse width is by negligence determined to be larger than PWM period; and
- In this application, the timer TMR2 Postscaler cannot be used for generating longer PWM periods.
PWM Resolution
PWM signal is nothing more than the pulse sequence with varying duty cycle. For one specified frequency (number of pulses per second), there is a limited number of duty cycle combinations. This number is called resolution measured by bits. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles etc. In relation to this microcontroller, the resolution is specified by the PR2 register. The maximal value is obtained by writing number FFh.PWM frequencies and resolutions ( Fosc = 20MHz):
| PWM Frequency | 1.22kHz | 4.88kHz | 19.53kHz | 78.12kHz | 156.3kHz | 208.3kHz |
|---|---|---|---|---|---|---|
| Timer Prescale | 16 | 4 | 1 | 1 | 1 | 1 |
| PR2 Value | FFh | FFh | FFh | 3Fh | 1Fh | 17h |
| Maximum Resolution | 10 | 10 | 10 | 8 | 7 | 6 |
Table 5-2 PWM Frequencies and Resolutions
PWM frequencies and resolutions ( Fosc = 8MHz):| PWM Frequency | 1.22kHz | 4.90kHz | 19.61kHz | 76.92kHz | 153.85kHz | 200.0kHz |
|---|---|---|---|---|---|---|
| Timer Prescale | 16 | 4 | 1 | 1 | 1 | 1 |
| PR2 Value | 65h | 65h | 65h | 19h | 0Ch | 09h |
| Maximum Resolution | 8 | 8 | 8 | 6 | 5 | 5 |
Table 5-3 PWM Frequencies and Resolutions
CCP1CON Register
Fig. 5-8 CCP1CON Register
| P1M1 | P1M0 | Mode |
|---|---|---|
| 0 | 0 | PWM with single output |
| Pin P1A outputs modulated signal. Pins P1B, P1C and P1D are port D input/output | ||
| 0 | 1 | Full Bridge - Forward configuration |
| Pin P1D outputs modulated signal Pin P1A is active Pins P1B and P1C are inactive | ||
| 1 | 0 | Half Bridge configuration |
| Pins P1A and P1B output modulated signal PinsP1C and P1D are port D input/output | ||
| 1 | 1 | Full Bridge - Reverse configuration |
| Pin P1B outputs modulated signal Pin P1C is active Pins P1A and P1D are inactive |
Table 5-4 CCP1CON Register
DC1B1, DC1B0 - PWM Duty Cycle Least Significant bits - are only used in PWM mode in which they represent two least significant bits of a 10-bit number. This number determines PWM signal’s duty cycle. The rest of bits (8 in total) are stored in the CCPR1L register.CCP1M3 - CCP1M0 - CCP1 Mode Select bits determine the mode of the CCP1 module.
| CCP1M3 | CCP1M2 | CCP1M1 | CCP1M0 | Mode |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | Module is disabled (reset) |
| 0 | 0 | 0 | 1 | Unused |
| 0 | 0 | 1 | 0 | Compare mode |
| CCP1IF bit is set on match | ||||
| 0 | 0 | 1 | 1 | Unused |
| 0 | 1 | 0 | 0 | Capture mode |
| Every falling edge on the CCP1 pin | ||||
| 0 | 1 | 0 | 1 | Capture mode |
| Every rising edge on the CCP1 pin | ||||
| 0 | 1 | 1 | 0 | Capture mode |
| Every 4th rising edge on the CCP1 pin | ||||
| 0 | 1 | 1 | 1 | Capture mode |
| Every 16th rising edge on the CCP1 pin | ||||
| 1 | 0 | 0 | 0 | Compare mode |
| Output and CCP1IF bit are set on match | ||||
| 1 | 0 | 0 | 1 | Compare mode |
| Output is cleared and CCP1IF bit is set on match | ||||
| 1 | 0 | 1 | 0 | Compare mode |
| Interrupt request arrives and bit CCP1IF is set on match | ||||
| 1 | 0 | 1 | 1 | Compare mode |
| Bit CCP1IF is set and timers 1 or 2 registers are cleared | ||||
| 1 | 1 | 0 | 0 | PWM mode |
| Pins P1A and P1C are active-high Pins P1B and P1D are active-high | ||||
| 1 | 1 | 0 | 1 | PWM mode |
| Pins P1A and P1C are active-high Pins P1B and P1D are active-low | ||||
| 1 | 1 | 1 | 0 | PWM mode |
| Pins P1A and P1C are active-low Pins P1B and P1D are active-high | ||||
| 1 | 1 | 1 | 1 | PWM mode |
| Pins P1A and P1C are active-low Pins P1B and P1D are active-low |
Table 5-5 Modes of Operations
CCP2 Module
Excluding the different names of registers and bits, this module is a very good copy of the CCP1 module setup in normal mode (previously discussed). There is only one true difference between their modes when CCP2 operates in Compare mode.That difference refers to the timer T1 reset signal. Namely, if A/D converter is enabled at the moment the values of the TMR1 and CCPR2 registers match, the timer T1 reset signal will automatically start A/D conversion.
Fig. 5-9 CCP2 Module
CCP2CON Register
Fig. 5-10 CCP2CON Register
CCP2M3 - CCP2M0 - CCP2 Mode Select bits select CCP2 mode.
| CCP2M3 | CCP2M2 | CCP2M1 | CCP2M0 | Mode |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | Module is disabled (reset) |
| 0 | 0 | 0 | 1 | Unused |
| 0 | 0 | 1 | 0 | Unused |
| 0 | 0 | 1 | 1 | Unused |
| 0 | 1 | 0 | 0 | Capture mode |
| Every falling edge on the CCP2 pin | ||||
| 0 | 1 | 0 | 1 | Capture mode |
| Every raising edge on the CCP2 pin | ||||
| 0 | 1 | 1 | 0 | Capture mode |
| Every 4th rising edge on the CCP2 pin | ||||
| 0 | 1 | 1 | 1 | Capture mode |
| Every 16th rising edge on the CCP2 pin | ||||
| 1 | 0 | 0 | 0 | Compare mode |
| Output and CCP2IF bit are set on match | ||||
| 1 | 0 | 0 | 1 | Compare mode |
| Output is cleared and CCP2IF bit is set on match | ||||
| 1 | 0 | 1 | 0 | Compare mode |
| Interrupt is generated, CCP2IF bit is set and CCP2 pin is unaffected on match | ||||
| 1 | 0 | 1 | 1 | Compare mode |
| CCP2IF bit is set, Timer 1 registers are cleared, A/D conversion is started if the A/D converter is on on match | ||||
| 1 | 1 | x | x | PWM mode |
Table 5-6 CCP2CON Register
In short: Setup CCP1 module for PWM operation
In order to setup the CCP module for PWM operation, the following steps should be taken:- Disable the CCP1 output pin. It should be configured as input;
- Set the PWM period by loading the PR2 register;
- Configure the CCP module for the PWM mode by combining bits of the CCP1CON register;
- Set the PWM signal’s duty cycle by loading the CCPR1L register and using bits DC1B1 and DC1B0 of the CCP1CON register;
- Configure and start timer TMR2:
- Clear the TMR2IF interrupt flag bit of the PIR1 register;
- Set the timer TMR2 prescale value by loading bits T2CKPS1 and T2CKPS0 of the T2CON register;
- Start the timer TMR2 by setting the TMR2ON bit of the T2CON register;
- Enable PWM output pins after one PWM cycle has been finished:
- Wait for the timer TMR2 overflow (TMR2IF bit of the PIR1register is set); and
- Configure the appropriate pin as output by clearing bit of the TRIS register.
CCP1 in Enhanced Mode
The enhanced mode is available on CCP1 only. Basically, this module does not differ from the one previously described and enhancement refers to transmission of PWM signal to the output pins. Why is it so important? Because the microcontrollers are more frequently used in control systems for electric motors. These devices are not described here, but if you ever have had a chance to work on development of similar devices, you will recognize elements which, until quite recently, have been used as external ones. Normally, all these elements are now integrated into the microcontroller and can operate in several different modes.Single Output PWM Mode
This mode is enabled only in the event that the P1M1 and P1M0 bits of the CCP1CON register are cleared. In this case, there is only one PWM signal which can be simultaneously available on a maximum of four different output pins. Besides, the PWM signal may appear in basic or inverted waveform. Signal distribution is determined by the bits of the PSTRCON register, while it's polarity is determined by the CCP1M1 and CCP1M0 bits of the CCP1CON register.When an inverted output is in use, the pins are low-active and pulses having the same waveform are always generated in pairs: on the P1A and P1C pins and P1B and P1D pins, respectively.
Fig. 5-11 Single Output PWM Mode
Half-Bridge Mode
In this mode, the PWM signal is output on the P1A pin, while at the same time the complementary PWM signal is output on the P1B pin. Such pulses activate MOSFET drivers in Half-Bridge mode which enable/disable current flow through device.
Fig. 5-12 Half-Bridge Mode
Fig. 5-13 Half Bridge Mode
Fig. 5-14 Activate MOSFET drivers
Full-Bridge Mode
In Full-Bridge mode, all four pins are used as outputs. In practice, this mode is commonly used to run motors, which provides simple and complete control of speed and rotation direction. There are two such configurations: Full Bridge-Forward and Full Bridge-Reverse.
Fig. 5-15 Full-Bridge Mode
Full Bridge - Forward Configuration
In Forward mode the following occurs:- Logic one (1) appears on the P1A pin (pin is high-active);
- Pulse sequence appears on the P1D pin; and
- Logic zero (0) appears on the P1B and P1C pins (pins are low-active).
Fig. 5-16 Forward Mode
Full Bridge - Reverse Configuration
The same occurs in Reverse mode, except of the pins functions:- Logic one (1) appears on the P1C pin (pin is active-high);
- Pulse sequence appears on the P1B pin; and
- Logic zero (0) appears on the P1A and P1D pins (pins are active-low).
Fig. 5-17 Reverse Mode
PWM1CON Register - STRC PWM Restart Enable bit
- 1 - Upon auto-shutdown, the PWM module is automatically reset, while the ECCPASE bit of the ECCPAS register is cleared.
- 0 - In order to restart PWM module upon auto-shutdown, the ECCPASE bit must be cleared in software.
Fig. 5-18 PWM1CON Register
PSTRCON Register
STRSYNC - Steering Sync bit determines the moment of PWM pulse steering:- 1 - Steering occurs upon the PSTRCON has been changed, but only if a PWM waveform is completed; and
- 0 - Steering occurs upon the PSTRCON register has been changed. The PWM signal on output pin is immediately changed with no regard to whether the previous cycle is completed or not. This operation is useful when it is needed to immediately remove a PWM signal from the pin.
- 1 - P1D pin has the PWM waveform with polarity controlled by the CCP1M0 and CCP1M1 bits; and
- 0 - Pin is configured as general Port D input/output.
- 1 - P1C pin has the PWM waveform with polarity controlled by the CCP1M0 and CCP1M1 bits; and
- 0 - Pin is configured as general port D input/output.
- 1 - P1B pin has the PWM waveform with polarity controlled by the CCP1M0 and CCP1M1 bits; and
- 0 - Pin is configured as general port D input/output.
- 1 - P1D pin has the PWM waveform with polarity controlled by the CCP1M0 and CCP1M1 bits; and
- 0 - Pin is configured as general port Ainput/output.
ECCPAS Register
Fig. 5-19 ECCPAS Register
- 1 - CCP module is in Shutdown state; and
- 0 - CCP module operates normally.
| ECCPAS2 | ECCPAS1 | ECCPAS0 | Shuthown state source |
|---|---|---|---|
| 0 | 0 | 0 | Shutdown state disabled |
| 0 | 0 | 1 | Comparator C1 output change |
| 0 | 1 | 0 | Comparator C2 output change |
| 0 | 1 | 1 | Comparator C1 or C2 output change |
| 1 | 0 | 0 | Logic zero (0) on INT pin |
| 1 | 0 | 1 | Logic zero (0) on INT pin or comparator C1 output change |
| 1 | 1 | 0 | Logic zero (0) on INT pin or comparator C2 output change |
| 1 | 1 | 1 | Logic zero (0) on INT pin or comparator C1 or C2 output change |
Table 5-7 ECCPAS Register
PSSAC1, PSSAC0 - Pins P1A, P1C Shutdown State Control bits define logic state on output pins P1A and P1C when CCP module is in shutdown state.| PSSAC1 | PSSAC0 | Pins logic state |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | X | High impedance (Tri-state) |
Table 5-8 A&C Logic States
PSSBD1, PSSBD0 - Pins P1B, P1D Shutdown State Control bits define logic state on output pins P1B and P1D when CCP module is in shutdown state.| PSSBD1 | PSSBD0 | Pins logic state |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | X | High impedance (Tri-state) |
Table 5-9 B&D Logic States
